Hybrid Fault Tolerance Techniques to Detect Transient Faults in Embedded Processors

Hybrid Fault Tolerance Techniques to Detect Transient Faults in Embedded Processors

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This book describes fault tolerance techniques based on software and hardware to create hybrid techniques. They are able to reduce overall performance degradation and increase error detection when associated with applications implemented in embedded processors. Coverage begins with an extensive discussion of the current state-of-the-art in fault tolerance techniques. The authors then discuss the best trade-off between software-based and hardware-based techniques and introduce novel hybrid techniques. Proposed techniques increase existing fault detection rates up to 100%, while maintaining low performance overheads in area and application execution time.In order to do that, the Inverted Branches software-based technique, described in Sect. ... By removing the reset present in PODER, for example, the beginning of a BB does not have any initialization and therefore is equal to any otheranbsp;...


Title:Hybrid Fault Tolerance Techniques to Detect Transient Faults in Embedded Processors
Author: José Rodrigo Azambuja, Fernanda Kastensmidt, Jürgen Becker
Publisher:Springer - 2014-07-07
ISBN-13:

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